Mobile radio frequency (RF) chip designs (e.g., mobile RF transceivers), including high performance diplexers have migrated to a deep sub-micron process node due to cost and power consumption considerations. The design of such mobile RF transceivers becomes complex at this deep sub-micron process node. The design complexity of these mobile RF transceivers is further complicated by added circuit functions to support communications enhancements, such as carrier aggregation. Further design challenges for mobile RF transceivers include analog/RF performance considerations, including mismatch, noise, and other performance considerations. The design of these mobile RF transceivers includes the use of additional passive devices, for example, to suppress resonance, and/or to perform filtering, bypassing, and coupling.
The design of these mobile RF transceivers may include the use of silicon on insulator (SOI) technology. SOI technology replaces conventional silicon substrates with a layered silicon-insulator-silicon substrate to reduce parasitic device capacitance and improve performance. SOI-based devices differ from conventional, silicon-built devices because the silicon junction is above an electrical isolator, typically a buried oxide (BOX) layer.
The active devices on the SOI layer may include complementary metal oxide semiconductor (CMOS) transistors. The process flow for semiconductor fabrication of CMOS transistors is generally performed during front-end-of-line (FEOL) processes. The front-end-of-line processes may include the set of process steps that form the active devices (e.g., transistors). The FEOL processes include ion implantation, anneals, oxidation, chemical vapor deposition (CVD) or atomic layer deposition (ALD), etching, chemical mechanical polishing (CMP), and epitaxy.